Many arrangements have been suggested to minimize the effect of faulty memory elements within a computer system. In some systems, spare memory modules are switched in to replace modules containing faulty elements, in others this replacement is performed at byte, word, row or column level, and in others error correction techniques are employed.
An example of the first of these systems is shown in U.S. Pat. No. 4,150,528 (Inrig and Chapman). In that system a memory module is marked as a substitute module which, on detection of a fault in any other module, responds to addresses ordinarily directed to the faulty module. An example of a system which operates at a less than full module level is shown in U.S. Pat. No. 4,527,251 (Nibby, Goldin and Andrews). In that system, a static memory stores a map showing the faulty areas of a random access memory, this map being generated in response to memory testing. In operation, the map is employed to avoid faulty areas in the random access memory. Error correction systems for correcting data read from faulty memory locations are shown in U.S. Pat. Nos. 3,436,734 (Pomerene and Melville) and 4,251,863 (Rothenberger).
None of these prior art systems includes an arrangement in which, if a fault is detected in a memory block defined by the lowest value addresses, that block is disabled and these addresses are employed to access the memory block previously defined by the set of addresses immediately above the lowest value addresses. Thus, the total memory is reduced by the memory in the disabled memory block.
This arrangement is highly advantageous in a system in which the lowest order memory block is soldered or otherwise fixedly attached to the planar circuit board of the microcomputer in order to minimize basic cost. These low order memory locations are used to store control program data and without them the system can not work. On the other hand this soldered memory is not normally replaceable, the usual service being to replace the complete planar circuit board on detection of a fault therein. Accordingly, by remapping the low order locations to pluggable memory, the system can still operate without planar board replacement.